With the development of the Internet of Things technology, many embedded systems have the need to increase Wi-Fi characteristics, such as using the built-in Wi-Fi of the smartphone to remotely control various embedded devices, enabling machine-to-machine communication (M2M). Embedded network solutions with IoT communication capabilities, and these will become mainstream requirements in the future. In the product design, considering the cost and other factors, ASIX Electronics' single-chip TCP/IP processor AX22001/11 can be used to design the Wi-Fi system. The AX22001/11 processor provides a cost-effective embedded network solution for a wide range of embedded applications that require simple, easy-to-use, low-cost access to wired/wireless LAN or the Internet.
1 single chip TCP/IP microprocessor AX22001/111.1 Basic performance of AX22001/11
The structure and characteristics of AX22001 and AX22011 are basically the same, the only difference is that AX22001 does not have external memory interface, the number of GPIOs is different (the number of GPIOs of AX22001 and AX22011 are 32 and 64 respectively) and the package form is different (the package type of AX22001 and AX22011) They are available in a 128-pin LQFP package and a 180-lead LFBGA package. This article uses AX22011 as an example to illustrate its basic features.
AX22011 is a single-chip TCP/IP microprocessor with built-in 802.11 wireless network MAC/baseband. It provides a high-performance dual CPU core and 1MB shared flash for code storage, while embedding 64KB of data for the main processor (MCPU). Memory and 32KB data memory for Wi-Fi processor (WCPU), while built-in TCP/IP accelerator compatible with 802.11a/b/g wireless network MAC/baseband, Fast Ethernet MAC and rich communication peripherals, available For all types of equipment that need to access wired/wireless Ethernet, LAN/Internet.
The AX22011 uses a dual CPU architecture and uses the MCPU to run applications and TCP/IP protocols. The WCPU handles the conversion of WLAN protocols and Ethernet to WLAN packet formats. The built-in WLAN MAC and baseband processor are IEEE 802.11a/b/g compliant and support 802.11 security features and 802.11e QoS features, as well as support for AP-based networks or peer-to-peer networks (Ad-Hoc/IBSS).
AX22011 can be used as a core chip to build applications, as well as through the TCP/IP protocol running on the chip and various parallel/serial interfaces (such as LOCal Bus, high-speed UART and high-speed SPI), as a network coprocessor to match other embedding. CPU to ease the load on TCP/IP and WLAN protocols.
1.2 Independent characteristics of AX22001/11
(1) Dual CPU architecture.
The dual CPU architecture of the AX22001/11 can be used for application and WLAN protocol processing, respectively.
The CPU uses 8-bit pipeline and reduced instruction set RISC, single instruction cycle, up to 80MHz main frequency, instruction set 100% compatible with standard 8051/80390; chip built-in power management unit and programmable watchdog timer and three 16-bit timing / Counters, millisecond timers, and real-time clock (RTC) controllers support CPU debugging via the In-Circuit Emulation Interface (ICE).
(2) The main processor.
The main processor (MCPU) is used for application and TCP/IP processing. The AX22001/11 provides a DMA engine (7DMA channel) and a dedicated memory architecture for fast data transfer of networks and peripherals while supporting TCP/IP hardware acceleration for increased network transmission bandwidth and IP implementation via hardware. /TCP/UDP/ICMP/IGMP checksum calculation and ARP protocol processing.
Protocols such as TCP, UDP, ICMP, IGMP, IPv4, DHCP, BOOTP, ARP, DNS, SMTP, SNTP, uPNP, PPPOE and HTTP provided by the software can support networks through Wi-Fi or Ethernet, BOOTP and TFTP protocols. Startup; support 2 external interrupt sources at the same time, and support 2 priority levels.
(3) Program and data memory.
AX22001/11 has built-in 16KB SRAM for program image, and 1MB of flash memory for MCPU and WCPU shared program code space. The chip supports in-system programming (ISP), which can be used for flash memory through UART or in-circuit debugger (ICE). Programming; support for programming applications via Wi-Fi, Ethernet or serial port and update startup code, ie Programmable in Application (IAP).
At startup, you can choose to copy the MCPU application code to run in external SRAM to improve system performance.
In addition, the AX22001/11 also has a built-in 64KB data memory for the MCPU that can be expanded to a maximum of 2MB through an external memory interface, while a 32KB data memory for the WCPU is built in.
(4) Wi-Fi processor and baseband controller.
The Wi-Fi processor in the AX22001/11 and its 802.11a/b/g compliant wireless network MAC/baseband controller support infrastructure infrastructure mode or Ad-Hoc peer-to-peer network mode (IBSS); support for both DSSS and CCK : 1, 2, 5.5, and 11 Mb/s; also supports OFDM: 6, 9, 12, 18, 24, 36, 48, and 54 Mb/s; supports 802.11i security features as follows: 64/128 WEP, TKIP, AES; Also supports 802.11eQoS and 1TX queues, but optional AC is the user's application data; the chip integrates RXIQ ADC, TXIQ DAC and TSSIADC, which can be used to connect RF transceivers; also supports between MCPU data memory and WCPU data memory and WCPU Data memory and WLAN MAC are converted between Ethernet and Wi-Fi packet format by DMA; also supports series Wi-Fi management frame and hardware acceleration, such as: MIC, SHA-1/MD-5 conversion, AES key expansion, Pseudo-random number generation (PRNG) and hardware implementation of 32-bit algorithm; in addition, it supports three Wi-Fi power-saving modes and can automatically wake up by receiving Beacon frames; in addition, AX22001/11 also provides one for WCPU debug serial port, 1 external interrupt pin and 1 I2C bus interface.
(5) 10/100M Fast Ethernet MAC.
AX22001/11 is compatible with IEEE 802.3 10Base-T/100Base-TX Fast Ethernet specification, built-in dedicated 12KBSRAM for packet buffer; supports full-duplex flow control and half-duplex backpressure flow control (backpressure); and provides MII , RMII, Rev-MII and Rev-RMII interfaces; in addition, it also supports Ethernet remote wake-up.
(6) Peripheral communication interface.
The AX22001/11 chip has 4 serial ports, 2 of which support DMA. The modem control pin supports remote wake-up and up to 921.6Kb/s baud rate; the chip supports DMA's fast SPI interface (including 3 main mode interfaces or 1) Slave mode interface) and an I2S or PCM interface supporting DMA, also supports DMA local bus interface (master/slave mode) and an I2C interface (master/slave mode); the chip has a 5-channel programmable counter group and a 1-Wire bus interface, providing 4 groups of GPIOs with 8 bits each; integrated 32.768kHz oscillator circuit (with independent power supply pin) for automatic wake-up timer for real-time clock and Wi-Fi power saving mode In addition, the chip integrates an 80MHz phase-locked loop, which can be connected to a 40MHz crystal oscillator. It also integrates a power-on reset circuit. The AX22001/11 chip is packaged in a 128-pin LQFP and is RoHS compliant. The operating temperature range is 0°C~+. 70 ° C.
1.3 Composition of AX22001/11
The chip consists of a main processor (MCPU), Wi-Fi coprocessor (WCPU), 64KB of data RAM, 16 KB of program RAM, 1MB of shared memory, clock and timer, TCP/IP acceleration engine, DMA engine, Ethernet MAC 802.11a/b/g wireless network MAC/baseband and ADC/DAC, SPI serial bus, serial port, I2C bus and local bus.
Figure 1 Block diagram of AX22001/11
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