introduction
With the rapid development of information science, people have more and more requirements on the signal form after data collection, and a single signal form has no way to meet the needs of actual engineering. Network signals, USB bus signals, RS232 bus signals, and CAN bus signals are currently widely used bus forms, but there is still a problem with the interchange between them, which has been limited by complex network protocols. However, the conversion of network signals can only be achieved through complex algorithms, so it cannot meet the occasions with high requirements on timeliness and realism.
1 Overall system design
The network signal conversion platform based on CO2128 devices presented in this paper mainly realizes the conversion between CAN bus, RS232 bus, USB bus and network ports through the ports provided by CO2128. Under the premise of ensuring the accuracy of the data, reducing the system overhead and increasing the speed is the focus of this design. Through the design, a medium / large-scale remote monitoring / data transmission network can be formed, in which the function of the CAN-Ethernet device is to realize the "transparent" transmission of data from the CAN bus to the Ethernet data. The overall structure of this design is shown in Figure 1.
Figure 1 overall system framework.
2 Hardware design
2.1 Introduction to CO2128
CO2128SEC firmware can support 10 simultaneous active TCP / UDP Socket connections, two listening sockets and one encrypted SSL3 / TLS1 Socket. Its encryption features include a hardware random number generator, SHA-1 / 256 encryption Hash accelerator, AES-128 / 192/256 encryption accelerator, 3DES and SSL3 / TLSI, WEP, WPA and WPA2 WiFi encryption. It also configures routing IP packets between LAN / WiFi and PSTN / GRPS / CDMA. In this mode called iRouter, multiple iChip can form an ad-hoc network without AP.
CO2128SEC can save the Internet protocol stack and configuration parameters in the memory of the main processor. The firmware can be run from the CO2128SEC external SPI Flash. The firmware can also be loaded via RS-232, two-wire interface, SPI or USB. The chip includes a 32-bit ARM7TDMI RISC processor core, 256KB of SRAM, and BUS that can access external memory or communication devices. It also integrates a BootLoader and can load firmware from the main processing system through the interface. CO2128SEC's peripheral equipment includes 10/100 BaseT Ethernet MAC with RMII, USART, two SPI, two-wire interface, HPI and EBI high-speed parallel interface. In addition, it also has a variety of energy-saving working modes.
The iChipSec CO2128 device overcomes all the complex obstacles of encrypted end-to-end IP communication. It does not require a large number of program adaptations. Because CO2128 uses AT + i API, the WiFi driver, security encryption, and network protocol loads are unloaded from the host device, thereby greatly reducing the burden on the main processor. CO2128 can support LAN, WiFi and all dial-up Internet / wireless network access types. It has built-in fully secure TCP / IP protocol stack and upper layer protocols (such as SMTP, POP3, MIME, HTTP, WAP, FTP and Telnet). At the same time, it contains a complete Web server, which can be used for chip parameter configuration and simple application management. The chip can use ten simultaneous TCP / UDP Sockets and two listening Sockets as well as POP3, SMTP, MIME, FTP, Telnet, HTTP / HTTPS clients, and supports SerialNET mode.
And in this mode, iChip can intercept AT + i commands and let the main device enter the Internet mode. After that, iChip will transparently send any AT commands from the master device to the communication device.
2.2 DM9161 transceiver
DM9161 is a 100 / 10M adaptive fast Ethernet physical layer single-chip transceiver, which can support automatic routing and automatic protocol selection. At the same time, since it has a network filter that needs to be trimmed inside, there is no need to add a filter to its peripheral circuits, which can reduce external auxiliary circuits.
2.3 DSP chip
The DSP used in this design is TI's TMS320LF2407. This DSP has SCI and CAN bus interfaces, and can quickly achieve the conversion of two signals through a simple program. TMS320LF2407 adopts high-performance static CMOS technology, the power supply voltage is 3.3 V, so it can reduce the power consumption of the controller.
The execution speed of 30MIPS shortens the instruction cycle to 33 ns, thereby improving the real-time control capability of the controller.
But when designing the network interface, pay attention to the layout of the signal lines on the PCB. Generally, the network transformer should be placed as close as possible to the DM9161 and RJ45 sockets, and the distance to the DM9161 cannot exceed 20 mm; the 50Ω termination resistance should be placed as close as possible to the network transformer and the RX +-, TX +-pins of the DM9161. The 50 ohm resistor and the grounding capacitance of RX and TX should be placed near DM9161, and should not exceed 10 mm; 25 MHz crystals cannot be placed around important signals. The trace from the RX of DM9161 to the network transformer and RJ45 must be symmetrical, direct, parallel and close together. Don't walk at right angles or 45 degrees. When using RX and TX, avoid using vias. The RX, TX, CLK and power traces should be as short as possible. RX and TX can not cross, the distance should be more than 3 mm, it is best to lay a ground wire between them. Do not take any digital lines from the RX and TX pairs of DM9161 to RJ45. Keep these two pairs of signals away from other signals and the ground. There must be no ground plane or power plane under the network transformer and RJ45. All RJ45 terminal pins (4, 5, 7, 8) and the network transformer must be close together and grounded through a resistor and 0.01 uF / 2 kV capacitor.
The BANDGAP resistor must be placed as close as possible to pins 47 and 48 (no more than 3 mm). Avoid placing any high-speed signals near this resistor (to the crystal must be greater than 3 mm). Figure 2 shows the hardware circuit of the physical layer and network interface of this system.
Figure 2 Hardware circuit of physical layer and network interface.
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