1. The function and characteristics of Godson 2F processor
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The Loongson 2F (LOONGSON-2F) processor used in this system is a universal RISC micro processor for the 64-bit MIPSIII instruction set recently released by the Institute of Computing Technology of the Chinese Academy of Sciences. The processor is the first in China to adopt a 90nm CMOS design process with an area of ​​35nm2. The measured power consumption is 4~5W at a typical operating frequency of 800MHz, and the maximum operating frequency is up to 1G. The highest floating point operation speed is 40/8 billion times per second. Dual/single-precision floating-point operation, on-chip integration of IO controllers such as PCI/PCIX, and integration of on-chip secondary CACHE, DDR2 memory controller, is very suitable for high-end embedded scale.
2. Structural framework of system hardware structure design system
The Loongson 2F (LOONGSON-2F) processor is the control center of the entire system and bears the mission of the rare data. The system generates the clock required by each chip on the motherboard via the ICS950220 clock synthesizer, and the chip has a watchdog function. The system memory is extended by the DDR2 controller integrated in the process processor. Taking into account the PCB board area and the higher bandwidth requirements for memory access, the memory capacity of the four-bit 16-bit wide memory is determined by the granularity. Capacity, up to 1GB of memory, operating at 300MHz. The LOCAL BUS extended 512KB Flash ROM supplied via the processor is used for system BIOS storage.
2.1 system power supply
Whether it is a car or a portable device, it needs to be powered by a DC power supply. Therefore, energy saving and high efficiency are the subject of power supply design. As shown in the power module of Figure 1, the system board uses a +5V DC adapter as the power supply. The 1.2V supplied to the CPU and the 3.3V DC power supply used in the supply interface circuit are efficient because of the current flowing through the system. Higher switching power supply. According to the conventional design, the 1.8V power supply for DDR2 and SM502 is introduced by the 3.3V power supply, and the bifurcation is generated by two linear power supplies (LDOs). The system is changed to a higher efficiency switching power supply, which improves the efficiency of the whole system. The measured power consumption of the entire system is controlled within 10W.
2 system interface
1. The system drives various interfaces through the multi-function display control chip SM502. The SM502 can be directly connected to the processor via the PCI BUS to support 2D display acceleration. It can supply: AC97-scale audio interface (via ALC203 chip control), one UBS1 .1 interface, a scale RS232 serial port and a debug serial port (both controlled by SP3232 chip), VGA and LCD display interface, ZV video interface (controlled by SSA7118 chip).
2. The system uses the RTL8139D as the Ethernet control chip through the PCI BUS to supply the 10/100M Ethernet interface. 3. The system uses the uPD720102 as the USB controller chip through the PCI BUS to supply three USB2.0 interfaces. One of the USB interfaces is supplied to an SD/MMC interface via the AU6331 reader controller chip.
3. system software
The system runs under the LINUX DEBIAN4.0 operating system and its kernel is LINUX 2.6.21. Bootoarder–PMON2000 is burned in the onboard BIOS ROM, and the initialization of the processor, cache, memory controller, and collection controller is automatically completed after power-on. At the same time, PMON2000 has a small number of row call sets, which are used for reading and writing verification of memory, flashing of onboard flash, IP setting, serial port setting and data communication with the host after uploading, collecting uploading, downloading files, receiving host Release instructions and so on. The LINUX 2.6.21 kernel is loaded into memory via an internal call to PMON2000.
There is a ROM on the memory stick, which retains information such as the memory size, the number of row addresses, the number of column addresses, and the number of banks in the memory. This information can be accessed via the I2C bus. As a general design scheme, it is required to support various types of memory modules. During the debugging process of the system, we found that the I2C logic of the SM502 chip has a bug. The SM2's gpio is used to simulate the I2C timing to read the memory (DIMM) strip information. And the operation of the read information to set up the DDR2 controller of the Godson 2F processor, received a brilliant end. It has been tested that the system now supports all types of memory modules on the market.
4. Signal integrity design
Because the entire system module circuit is small in size, and the operating frequency of the circuit is high, there is a severe requirement for the integrity of the signal for the entire design. The DDR2 memory of the Godson 2F processor operates at a frequency of up to 300MHz. This circuit is a bottleneck in the design of high-speed circuits. The power of the circuit simulation in this sector can reflect the transmission of the entire circuit signal. The DDR2 control signal is taken as an example to describe the design and process adopted in this problem.
In the actual design, firstly, the IBIS mold and simulation tool [4] of the Godson 2F are pre-determined to determine the routing topology and matching system of the signal, thereby formulating the constraints of the PCB wiring. Firstly, the simulation model before the PCB wiring is extracted, and the corresponding simulation power waveform can be observed through the process, and the topology of the trace and the matching circuit parameters for obtaining the better signal quality can be determined. After completing the PCB layout, the real topology is extracted and simulated. The extracted topology is shown in Figure 3. At this point, the mold has collected the stacking and impedance control information of the PCB and modeled the actual via. Adjusting the traces through the process is not a good way to see the simulation power to get the final best trace. Figure 4 shows the effect of the adjusted simulation. It can be seen that the better quality of the signal is obtained on the receiver, and the overshoot of the driver is also within the scale of the takeover. Finally, in the actual board debugging, the actual signal waveform is measured again, and the matching components are finely adjusted to ensure the reliability of the actual signal quality. Practice has shown that based on this system and process, it can reduce the design risk caused by the integrity of the signal and reduce the difficulty of debugging. All simulation IC modeling parameters in this document are typical, and the driver's excitation signal is 133MHz period signal.
6. summary
This paper introduces the design process of the vehicle and portable equipment system based on the Godson 2F processor. It first elaborates on the hardware structure of the system, the software system, the integrity design of the signal, and the improvement of the efficiency of the whole machine. The system is compact in structure, and it can work both self-reliantly and flexibly. It has a great application prospect.
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