In the current embedded application development process, C language has become the best choice for most occasions. As a result, the main function seems to be the starting point of course - because C programs often start from the main function. But one problem that is often overlooked is: How does the microcontroller (microcontroller) find and execute the main function after power-on? Obviously, the microcontroller cannot locate the entry address of the main function from the hardware. Because the C language is used as the development language, the address of the variable/function is allocated by the compiler at compile time, so that the entry address of the main function is micro. The Controller's internal storage space is no longer absolutely constant. I believe that readers can answer this question. The answer may be similar, but there must be a keyword called " startup file ", which is described as " bootloader " in English words.
Regardless of high performance, simple structure, and high price, each type of microcontroller (processor) must have a startup file. The function of the startup file is to execute the microcontroller from "reset" to "start executing main function". The work that must be done during this period of time (called the startup process). The most common 51, AVR or MSP430 microcontrollers also have corresponding startup files, but the development environment often provides this startup file automatically and completely, without the need for developers to intervene in the startup process, only need to start the application from the main function. The design is all right.
About "Startup Mode"
The topic goes to the STM32 microcontroller. Whether it is keil uvision4 or IAR EWARM development environment, ST company provides ready-to-use boot files that can be directly used. Program developers can directly import C files and directly develop C applications. This can greatly reduce the developer's jump from other microcontroller platforms to the STM32 platform, and it also reduces the difficulty of adapting to the STM32 microcontroller. (For the previous generation ARM's masterpiece, the startup file is often the first hard but it is difficult. Unsurpassable hurdles). Compared with ARM's previous generation of mainstream ARM7/ARM9 core architecture, the startup mode of the new generation Cortex core architecture has undergone considerable changes. After the ARM7/ARM9 core controller is reset, the CPU will start by taking the first instruction to execute the reset interrupt service routine from the absolute address 0x000000 of the memory space, that is, the start address after the reset is fixed is 0x000000 (PC =0x000000). At the same time, the position of the interrupt vector table is not fixed. The Cortex-M3 core is just the opposite. There are three cases:
1. The interrupt vector table can be located in the SRAM area by the boot pin setting, that is, the starting address is 0x2000000, and the PC pointer is located at 0x2000000 after resetting;
2. The interrupt vector table can be located in the FLASH area by the boot pin setting, that is, the starting address is 0x8000000, and the PC pointer is located at 0x8000000 after resetting;
3. The interrupt vector table can be located in the built-in bootloader area through the boot pin setting. This article does not discuss this situation;
The Cortex-M3 core specifies that the start address must hold the top-of-stack pointer, while the second address must hold the reset interrupt entry vector address, so that after the Cortex-M3 core is reset, it will automatically be from the next 32-bit space of the start address. The reset interrupt entry vector is fetched and the jump is executed to reset the interrupt service routine. Compared to the ARM7/ARM9 core, the Cortex-M3 core fixes the location of the interrupt vector table and the starting address is changeable.
Details the startup process of STM32
The following is from the ST startup file, because the startup_stm32f10x_md.s in the library is related to the compilation environment, so it is for the library.
The files in the STM32F10x_StdPeriph_Lib_V3.5.0\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\TrueSTUDIO path are analyzed.
System_stm32f10x.c
SystemInit(): is called in the "startup_stm32f10x_xx.s" file. The function is to set the system clock (including the clock source, PLL coefficient, AHB/APBx prescaler coefficient and flash setting). This function will reset the system. It is then executed first. Some default settings in the file: Allow HSE (external clock), FLASH (allow prefetch buffer, set 2 wait cycles), PLL coefficient is 9, turn on PLL and select PLL output as clock source (SYSCLK), then set SYSCLK = HCLK = APB2 = 72MHz, APB1 = HCLK/2 = 36MHz, HCLK is the AHB clock.
SystemCoreClockUpdate(): Called when the system clock HCLK changes to update a global variable SystemCoreClock, which can be used by the application and must be guaranteed to be correct. This function is not called by default because SystemCoreClock is set to the set frequency by default (72MHz)
In addition, the following method of setting a register is worth learning. First, clear the corresponding bit with the bit name, and then set it, for example:
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*! PLL entry clock source */
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*! HSE divider for PLL entry */
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*! PLLMUL[3:0] bits (PLL mulTIplicaTIon factor) */
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*! HSE clock selected as PLL entry clock source */
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*! PLL input clock*9 */
/* PLL configuraTIon: PLLCLK = HSE * 9 = 72 MHz */
RCC-"CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC-"CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
Startup_stm32f10x_md.s: (for F103RBT6 medium capacity products)
This file first defines the processing function of reset interrupt (reset entry vector is fixed by hardware at address 0x0000_0004): Reset_Handler, its function is to copy the initialization data stored in flash to sram, call SystemInit mentioned above to initialize Clock, then jump to main execution.
Then define Default_Handler, this is the default processing function for all other interrupts, the role is an infinite loop, so if you open an interrupt, please write interrupt processing function according to the interrupt function name, such as serial interrupt processing function The name is USART1_IRQHandler, you open the serial port interrupt, if you do not rewrite USART1_IRQHandler, the default implementation of Default_Handler, infinite loop. And if you have a rewrite, the address of the handler in the interrupt vector table is updated to the address of the function you wrote yourself. Why is this so? Because a statement like this is used at the end of this file:
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
It provides a weak alias (Default_Handler) for the interrupt handler. If it is not overridden, the default execution of Default_Handler is interrupted. If it is overridden, it is overridden by a function of the same name that you wrote.
Finally, a segment of the interrupt vector table (.secTIon .isr_vector, "a", %progbits) is defined. This table will be placed at 0x0000 0000. The second word (0x0000 0004) is the reset vector. The function referred to is executed.
So, how do you ensure that the .isr_vector section will be placed at the very beginning of the flash (0x08000000)? This requires a link script, that is, the stm32_flash.ld file we used. Check it out, and define the address of the stack first:
_estack
/* Highest address of the user mode stack */
_estack = 0x20005000; /* end of 20K RAM */
Then define the size of the heap and stack:
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x100; /* required amount of stack */
Then declare the area of ​​each memory (defined a few names that represent a linear space, such as the following FLASH):
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K }
Then I will introduce the above three names in the above, first of all, FLASH:
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4); } â€FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4); *(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4); _etext = . ; /* define a global symbols at end of code */
} 》FLASH
You can see that the section .isr_vector defined in startup_stm32f10x_md.s is indeed at the very beginning.
But we said earlier that the reset vector is at 0x0000 0004, and now its address is in flash, so the address is 0x0800 0004, what is going on? Originally, stm32 can map flash to 0x0000 0000 through the configuration of boot0 and boot1 pins. For details, refer to section 2.4 of the stm32 user manual.
Boot from main flash memory (BOOT0 = 0, BOOT1 = X): The main flash memory is mapped to the boot space (0x0000 0000), but can still access it at its original address (0x0800 0000), ie the contents of the flash memory can Accessed in two address areas, 0x0000 0000 or 0x0800 0000.
At this point, the startup process and program structure of the entire STM32 can be relatively clear.
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