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At present, the shooting, production, transmission and broadcast of TV programs are being digitized. The emergence of MPEG video and audio coding standards has solved the problem of excessive information and limited channel bandwidth after digitization of TV signals, and the continuous advancement of products in digital video hardware has promoted the launch of various digital video products, all of which indicate Television broadcasting has entered the era of digitalization. The development of digital TV products not only brings high-quality pictures and sound effects to the audience, but the development of ATM network access technology for MPEG-II video audio compression paves the way for the era of VOD (Video On Demand).
Currently, the world's digital TV system standards include the European DVB system and the US ATSC system. Both systems use the MPEG-II standard for video compression, the DVB system uses the MPEG-II audio compression standard for sound, and the ATSC system uses Dolby AC-3 compression technology. This article introduces C-Cube's MPEG-II encoder chip DVxpert-II, which can be used in the product development of the front-end system of the European DVB standard conventional digital TV.
1 chip introduction
The video processing single-chip DVxpert-II developed by C-Cube is a processor that improves performance based on the company's DVx MPEG-II single-chip encoding/decoding architecture. It produces high quality 4:2:0 and 4:2:2 MPEG-II images with an improved compression ratio. The chip can realize three functions of video encoding, decoding and codec, and can realize motion compensation and block/discrete cosine transform compression algorithm.
At the heart of the DVxpert-II processor is the 32-bit Micro SPACR RISC Core processor operating at 100mhZ. The processor has a 16K byte instruction cache (I-Cache) and an 8K byte Data Memory interface, which is a programmable and scalable architecture. The chip uses a data memory instead of a data buffer in order to allow the software to have more control over the memory and to allow repeated DMA transfers. In addition, the DVxpert-II processor has two coprocessors: the DSP coprocessor and the Motion Estimator, which alleviate the burden of the RISC processor. They jointly complete the video compression coding algorithm and improve the coding. speed. The DSP coprocessor can execute approximately 1.6 billion arithmetic operation instructions (1600 MOPS) per second, executing vector-to-memory-to-memory instructions, which can increase the speed of operation from RISC to DSP traffic. Its 8K byte memory has two buffers (two blocks) that allow the DMA and DSP to operate simultaneously.
The DSP coprocessor can perform the following functions: 1 solution TV movie mode; 2 activity measurement; 3 motion compensation; 4 adaptive temporal filtering; 5 linear filtering and filtering; 6DCT transform and inverse DCT transform (12 bits); Quantization; 8 variable length Huffman coding and decoding.
The Programmable Motion Estimation Coprocessor (Motion Estimator ME) supports all block matching and motion estimation types, which take motion estimation commands from the RISC processed CPU and return the results. An interrupt is generated each time the motion estimation is completed.
Many companies have their own single-chip MPEG-II encoded LSI. The circuit structure required for DCT and motion compensation calculations is different. The DVxpert-II chip developed by C-Cube is the "processor type" chip that is mostly processed by RISC processor and DSP. Also included is the software developed by C-Cube, a microcode (.ux) file. This file includes the code for video compression and the memory that initializes the DVxpert-II processor and the SDRAM that is external to the processor to be described below. Because of its programmable performance, you can change the compression algorithm or correct the software errors by changing the microcode input to the processor.
The internal block diagram of DVxpert-II is shown in Figure 1.
As can be seen from the figure, the DVxpert-II processor communicates with the host and other devices by using the PCI bus interface. The host must use the PCI bus to drive the processor to control the encoding process; the compressed video bit stream must also be stored to the host via the PCI bus. The PCI interface is driven by the host clock (33MHz).
The DVxpert-II processor also has an interface to the serial ROM, and the developer can choose to load a partial initialization program using the serial EPROM. In this development system, in order to simplify the hardware circuit, all the initialization processes are completed by the driver via the PCI bus interface (the serial EPROM can be omitted).
The chip can also be plugged into 64-bit synchronous dynamic RAM (SDRAM). The actual circuit uses four 16-bit SDRAMs to implement 8 Mbytes of external memory, stores C-Cube's microcode and data, and can be allocated storage space by developers. When the processor performs MPEG-II video encoding, the specific contents of the SDRAM are as follows: 1 application microcode; 2 video frame capture buffer; 3 motion estimation sampling video buffer; 4 predicted reconstructed frame buffer; Frame; 6 rate buffer; 7 local table and other data used to encode the algorithm.
The processor has a video interface for inputting/outputting uncompressed digital video streams, and an audio interface for inputting/outputting uncompressed digital audio (for information synchronized with the video). The DVxpert-II processor can only perform video encoding, while the uncompressed audio data can only be sent to the host memory via the PCI bus, and software compression is performed outside the DVxpert-II processor.
The development system performs video encoding of 4:2:0Main Level @ Main Profile, using only one DVxpert-II processor, so it can be used without the IPC interface connected to another processor.
2 driver development
The virtual device driver can contain device-specific code that operates on the device, the task has an operational mode, and the hardware device that needs to save the data needs a virtual device driver. The virtual device maintains the device state trajectory for each application and ensures that the device is in the correct state when the application continues to execute. The encoder integrates DVxpert-II into a plug-and-play PCI card, so the virtual device driver (VxD) of the PCI device is developed to support the normal operation of the encoder chip. The software is developed by Microsoft VC 6.0 in WIN98. Run under the operating system. The basic system architecture of the WIN98 operating system is divided into Ring0 layer and Ring3 layer, which can provide different levels of system protection. The Ring3 layer is separated from other running processes by the protection services provided by the Intel processor system for protection purposes. The Ring0 layer is composed of a virtual machine manager (VMM) or the like. VxD is a 32-bit executable program that manages system resources such as hardware devices or installed software. It runs on the Ring0 layer, handles system or peripheral interrupts, and DMA operations. It enables Windows-based applications to efficiently implement multitasking. WIN95/98's VxD provides support for plug and play, so when the DVxpert-II processor circuit is designed as a plug-and-play PCI expansion card, it can be automatically detected by the operating system after startup. VxD software development can be carried out using the VtoolsD for Win95 development kit from Vireo.Software, Inc., which is developed as a dynamically loadable/unloadable driver that resides in extended memory in protected mode. The Quick VxD program in VtoolsD provides options to quickly generate a VxD code framework. The encoder's VxD shall include: initialization of the device, processing of interrupt signals, and communication with the Run3 layer.
The initialization flowchart of the device is shown in Figure 2.
The microcode data can be transmitted to the encoder device via the PCI bus in two modes (slave mode and main mode). The slave mode can only transmit one 32-bit double word at a time, the speed is slow, and the main mode is bursted by DMA, which can transmit a large amount of data at high speed. The part of the microcode written to the processor control bus register can only be used in slave mode; the data in the SDRAM is written in the microcode. The ux file should be in DMA mode, which is implemented by setting some registers of the processor.
The memory of WIN95/98 is a smooth linear memory mode. The linear addressing mode simplifies the development process of the application software and provides the function of accessing the virtual address space, so that the user can access the memory address up to 4GB, 2GB to the application software, 2GB. For the operating system itself, VxD can apply for 4 BUFFERs for storing commands and messages used in DMA mode transmission encoding. The BUFFER indicates the continuous space of the physical address and can also be mapped to the corresponding linear address space.
The virtual device driver handles interrupts from the encoder while it is working. The service process is as follows:
1 first clear the interrupt; 2ISR stores the message in BUFFER to the message queue; 3ISR checks the serial number of the current message: if there is an error, go to the function that handles the error, if there is no error, ISR moves the next command in the command queue to Within the BUFFER of the Ring0 layer; 4 analyzes the new message in the message queue and writes the corresponding new command.
In WIN95/98, Win32API provides device input and output control (DeviceIoControl) to support direct call from Ring3 to Ring0, which is usually used to call dynamically loaded VxD; Ring0 layer can be passed to pDIOCParams->dioc_OutBuf in OnW32DeviceIoControl(PEOCTLPARAMSpDIOCParams) The Ring3 layer passes data.
The PCI interface and programming interface provided by DVxpert-II make it easy to integrate into a PC card and can be flexibly controlled by the driver. The VxD is currently in use and the encoder device works well.
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