In advanced process node semiconductor manufacturing, the variability of processes and devices cannot be ignored. At the process site of semiconductor manufacturing, advanced process control (APC) has been widely used to reduce and optimize process and device variability (between batches, between wafers, and within chips), increase manufacturing stability, and reduce manufacturing costs. These manufacturing variations will also affect wafer yield and product characteristics. Wafer-level probe testing (Chip Probing) is located after the semiconductor manufacturing process is completed, whether the chip circuit characteristics can be adjusted during the wafer probing stage to further resist the manufacturability variation in the advanced process and become the chip product design and DFY/DFT yield One of the hot spots of upgrading design. Aiming at the wafer-level probe test, the APC principle is applied in the circuit parameter adjustment test, and the advanced test control (ATC) concept is proposed. The parameter adjustment test of the traditional CP is optimized through the ATC algorithm, which greatly reduces the time and cost of the wafer probe test. The coverage rate of wafer probe test and product yield rate are improved.
1 Introduction
With the increasing demand for low-power and high-speed specifications in industrial and consumer electronics, Moore’s Law that drives semiconductor processes continues to evolve (65 nm, 40 nm, 28 nm...). The continuous shrinking of device size and the improvement of performance have caused the difficulty of semiconductor manufacturing process variability control and manufacturing stability to increase exponentially. Therefore, the continuous shrinking of the mass production process window of advanced semiconductor products is becoming an increasing challenge, as shown in Figure 1. Shown.
The process parameter variability in semiconductor manufacturing is an inherent characteristic. The process variability of lithography critical dimensions, film thickness, device doping concentration, etc., causes the parameter distribution of the same type of device to widen, as shown in Figure 2. The saturation current of the transistor under 65 nm is significantly higher than the saturation current dispersion under the same channel width dimension of the 130 nm process. The variability of this process and device will lead to deterioration of circuit characteristics and even abnormal operation, which has a direct impact on the parameter characteristics and yield of the final product [1].
In view of the inherent variability of semiconductor manufacturing processes, the semiconductor industry generally adopts APC (Advanced Process Control) systems at advanced process nodes to increase the control of process parameters. R2R control technology is a process control method widely used in semiconductor manufacturing [2,3] to reduce the manufacturing variability of important process parameters.
R2R (Run-to-Run) control strategy is a model-based process control algorithm for batch processes. Before the process of each batch, based on historical process information and current wafer information, it is more able to control the model, dynamically adjust the best recipe for wafer processing, and reduce the variation between batches. The APC control system of semiconductor manufacturing generally adopts R2R strategy, combined with traditional SPC control and FDC technology. R2R control algorithm has exponentially weighted moving average (EWMA) [4], model predictive control, MPC), etc., comprehensively reduce process manufacturing variability, reduce costs, and improve product yield and production efficiency. Figure 3 shows the R2R control structure diagram.
2 Programmable SoC product manufacturing process and performance requirements
The application scenarios of high-performance programmable SoC chips (MCU, DSP, FPGA, etc.) are more and more extensive, and the embedded flash memory process used to manufacture programmable SoC chips has also become one of the characteristic processes of semiconductor manufacturing [5]. The stable operation of the embedded flash memory requires a series of analog circuit modules to generate accurate analog signals to ensure the correct operation and reliability of the flash memory unit. These analog signals include: erasing high voltage, reference voltage, reference current, etc. Process variability will seriously affect the accuracy and repeatability of analog circuits. As the flash memory technology continues to shrink, the erasing window of the flash memory cell continues to shrink, and higher and higher requirements are put forward for the accuracy of the analog circuit for flash memory operation.
For embedded flash memory SoC products, in addition to the general use of APC systems in semiconductor manufacturing processes to reduce process and device variability, the analog circuits usually required for flash memory operations will also increase yield improvement designs (DFY/DFT), and flash memory operations are reserved The adjustment interval of auxiliary circuit parameters can appropriately cope with the circuit performance differences caused by semiconductor manufacturing variations [6]. In the wafer-level probe test, the operating parameters of the flash memory are adjusted by an automatic tester to achieve the required stable operating conditions of the flash memory.
Take an embedded flash memory product verified on 55 nm process as an example. In the circuit design, 32 adjustment gears can be reserved, and each gear can be adjusted at 0.07 V. This DFY design can compensate ±1.1 within the target range Manufacturing variation in circuit characteristics of V. In traditional wafer-level testing, circuit parameters are adjusted separately for each wafer and each chip, and the full range is traversed from the gear boundary to find the best gear that meets the target. Each wafer test is complete Independently, it is impossible to use wafer historical benchmark data, which results in long time for parameter adjustment and low efficiency.
In view of the lot to lot, wafer to wafer and die to die manufacturability variations in wafer manufacturing, this paper proposes the ATC concept and basic algorithm implementation of wafer probing , Based on the analysis of historical product characteristic data of tested wafers and chips, combined with the modeling and prediction of the adjustment behavior of the circuit to be tested, the scan boundary and algorithm are dynamically adjusted to reduce the parameter adjustment test time and improve the efficiency of wafer probing
3 Wafer-level parameter adjustment ATC algorithm
The wafer-level test ATC flowchart and constituent elements can be simply represented as shown in Figure 4.
The ATC control structure elements have the following groups.
(1) Circuit parameter adjustment target and behavior model. General analog circuit parameters such as high voltage, reference voltage and current DFY/DFT design, the change of these circuit parameters P is a function f-(x) of the adjustment gear x. f-(x) is generally a monotonic circuit behavior function. This function can be linear or non-linear, and can usually be simulated and estimated during the DFY/DFT design stage; the parameter adjustment target is set to tar, and x is adjusted to tar It can be expressed by f-1(tar): x = f--1(tar).
(2) Circuit parameter adjustment reference model and control algorithm. In this example, the inter-batch variation is not considered for the time being, and the inter-wafer and intra-chip variation are divided into two feedback control loops to form the ATC parameter adjustment adaptive test for wafer-level needle testing. The circuit parameter adjustment model and the adjusted gear can be expressed by formula (1) and formula (2).
Xi,j = f--1i,j (tar) (1)
S i,j = Xi,j-X-0 + 1 (2)
Where i is the current adjustment test wafer, j is the current adjustment chip, X-0 is the starting point of scanning, tar is the adjustment target, Xi,j is the target adjustment gear, and Si,j is the adjustment gear of the current chip number.
The traditional parameter adjustment method is full range parameter scanning, and the effective range of X-0 of each chip is X-min ~ X-max. In the circuit parameter adjustment algorithm proposed in this paper, X-0 is not a fixed value, but a dynamically updated reference scanning starting point Xr. The adjustment gear S i,j and the current reference scan starting point X r (i,j) can be expressed as formula (3) and formula (4).
S i,j = Xi,j- X r (i,j) (3)
(4)
jmax is the total number of chips on each wafer, and the starting point for adjusting the parameters of the current chip to be tested is X r (i,j) is the scanning starting point Xr(i-1,max) when the adjustment of the previous wafer is completed and the current i wafer has been adjusted The adjusted chip j-1 is the dynamic value calculated by ATC feedback of historical characteristic parameters such as the actual adjustment gears Xi, j-1. In formula (4), A is the weight of the influence of process variability on batch-to-batch and chip-to-chip circuit parameters.
(3) The parameter ATC scan starting point X r is updated. Initialize traversal parameters and parameter scan boundary;
(4) Parameter traversal algorithm controller. Based on whether the parameter adjustment behavior is linear, non-linear, monotonous and non-monotonic, choose the optimal algorithm: Generally, linear traversal or binary search is selected for monotonous circuit behavior, and the algorithm complexity is a function of the parameter maximum adjustment gear X max log2 (X max). For non-monotonic circuit behavior, generally use sequence to find whether there is a target match in the adjustment space.
(5) In the parameter adjustment traversal process, the circuit parameter gear k is set by the automatic test machine, and real-time measurement is performed. The parameter adjustment space traversal algorithm is shown in Figure 5. If the traversal is completed and no gear that meets the adjustment target is found, it is judged that the parameter adjustment has failed, Bin is divided and the test is stopped; if a gear that meets the target is found, the adjustment is successful.
(6) In-situ recording and feedback of the parameter adjustment gears Xi,j and parameter measurement value M-(k) of the current test chip, and feedback for the next test chip to update the parameter adjustment constraints.
(7) Offline SPC control and analysis for the optimal adjustment gear and parameter values ​​of the wafer, and regular correction of the weight factor A in the ATC parameter adjustment model. This can also be used as one of the indicators of the baseline drift of the semiconductor production line.
4 Wafer-level parameter ATC test algorithm implementation and performance analysis
In order to briefly explain the concept of ATC parameter testing, this article takes the production test of a 55 nm embedded flash memory chip that is about to enter mass production as an example: this wafer has 72 verification chip wafers, and the flash memory needs to be adjusted in the wafer-level test. Write high voltage to 4.5 V, the output high voltage adjustment function of this charge pump Vout = f(x) has 32 gears, so x has 0, 1, 2, 3… 31 effective discrete values. Traditional parameter scanning adjustment algorithm: the total number of adjustment steps per wafer is expressed as Stotal, the scanning starting point x starts from the minimum fixed value Xmin, and the total number of adjustment steps per wafer is expressed as formula (5).
Stotal = ∑j Si,j = ∑jmaxj=1[ fi,j (tar)-Xmin +1] (5)
The total scanning steps of the parameter adjustment algorithm based on the ATC concept can be expressed as formula (6).
Stotal =∑j [X i,j-Xr(i,j)]
= ∑jmaxj=1[ fi,j (tar)-Xr (i,j) +1] (6)
According to the wafer-level electrical parameter ATC feedback and adjustment algorithm proposed in Figure 4 and Figure 5, the development test program was tested in the erase and write high-voltage parameter adjustment test of a 55 nm advanced embedded flash memory product. The final gear distribution of a wafer after the traditional non-ATC adjustment test is shown in Figure 6 and Figure 7. According to the parameter adjustment target, after the high-pressure parameter is adjusted correctly, the gears are concentrated in the median value of 20, the largest gear is 25, and the smallest gear is 18, as shown in Table 1.
According to formula (5) and formula (6), the traditional parameter adjustment method and test cost on the experimental wafer is 1 487 steps, while the test cost based on the ATC algorithm adjustment is 249 steps, which is a year-on-year saving of 1,238 steps and a saving ratio of 83 %,As shown in table 2.
Under the same wafer probe test conditions, the reduction in the number of parameter adjustment steps can be directly equivalent to the reduction in unit test time. Therefore, the efficiency of the parameter adjustment test of the ATC concept will be significantly improved compared to the traditional test method. In the case of large-scale mass production testing, there are multiple items for product simulation parameter adjustment testing. Under the premise of ensuring the accuracy and coverage of wafer test parameter adjustment, the reduction of wafer test time and test cost will be very important. Considerable.
5 Conclusion
This paper proposes a wafer-level ATC test concept and applies it to the mass production probe test of advanced mixed-signal chips. At the same time, the basic ATC basic components and implementation algorithms are proposed. This algorithm is developed and verified on the industry's mainstream test platform for CP probing programs. The coverage and correctness of parameter adjustments have received good feedback during the development and production process.
Advanced mixed-signal SoC chips continue to evolve with Moore's Law, and the impact of chip manufacturing variability on product yield is becoming more and more important to ignore. The simultaneous application of front-end manufacturing APC and wafer probe ATC will play an increasingly important role in improving the yield of advanced processes and enhancing manufacturability.
80 Plus Bronze
Boluo Xurong Electronics Co., Ltd. , https://www.greenleaf-pc.com