Introduction: Continue to summarize some of the "fine details" in the process of learning digital circuits and share them with everyone.
1. In digital circuits, BJT generally works in the cut-off area or saturation area. The experience of the amplification area is only a fleeting process. The longer the process, the worse its dynamic performance. Similarly, the CMOS tube only works. In the cut-off zone or variable resistance zone, the experience of the constant current zone is only a very short process. Because we need the exact 0, 1 value, can not be too "ambiguous", otherwise the anti-interference performance between the gates in the digital system will be greatly reduced!
2. Many gate circuits in digital ICs generally connect many CMOS transistors in parallel, which can make its on-resistance small and improve its high-frequency performance.
3. In the digital circuit, the dynamic performance of the MOS tube, that is, the switching speed, is limited by the charging and discharging processes of the interelectrode capacitance. The smaller the capacitance, the faster the switching speed. Therefore, we need to take note of this when selecting pipes.
4. The quality and stability of the clock will directly determine the performance of the synchronous sequential circuit.
5, CMOS transmission gate is actually a voltage control switch that can transmit voltage signals (analog signals or digital signals), it can be used for multi-channel signal acquisition, sharing an ADC, but it also has the disadvantage that it transmits analog signals The noise is also transmitted, which should be well measured during the digital circuit design process.
6, because the CMOS circuit power consumption is very low, the internal heat is very small, so the integration can be done very high, which is an aspect that TTL circuit can not match.
7. The two BJTs that form the push-pull type in the output stage of the TTL inverter circuit are always turned on and the other is turned off, which effectively reduces the static power consumption of the output stage, thereby improving the ability to drive the load. The switching performance of the device has also been improved.
8. In the digital system design, we should pay attention to the influence of switching time and distributed capacitance of semiconductor devices (MOS tube and BJT), that is, the process of charging and discharging, which cannot be ignored. When the input signal changes, there must be enough The magnitude of the change and the time of action can change the state of the output. For example, in some clock flip-flops, the input signal must be established before the CP signal so that the circuit can be flipped reliably. It can be seen that when the frequency of the clock signal rises to a certain extent, the trigger is too late to flip.
9. It has been verified by predecessors that any combinational logic circuit is composed of its smallest term and can represent the standard form of the sum of the minimum terms.
10. After verification by the predecessors: Since the interference pulse is usually of the same order of magnitude as the transmission time of the gate circuit, in the TTL circuit, it is only necessary to connect a filter capacitor of several hundred pF at the output terminal to weaken the interference pulse. Below the door open level. As for how to verify, this process may be more elaborate, I still can't understand it.
11, the basic unit of the combinational logic circuit is the gate circuit, and the basic unit of the sequential circuit is a trigger, this concept should be well known. From this it can be inferred that the state of any sequential circuit is memorized and represented by the various flip-flops that make up the sequential circuit.
12. The latch using the capacitor storage method is actually an analog-valued sample-and-hold device. Due to the leakage current characteristic of the capacitor, we need to constantly refresh it and latch it through the positive feedback storage mode. This is not necessary.
13. The microcomputer interface and internal circuit are TTL and CMOS type circuits. These circuits cannot be directly connected to RS-232. Level conversion must be performed in the middle, such as adding an RS-232 chip.
14. The input signal driving the TTL circuit must have a fast conversion time. When the rise or fall time of the input signal is greater than a certain time (as generally described in the data sheet), signal oscillation may occur at the output.
15. For the PN junction of silicon material, the breakdown voltage is 7V, which is avalanche breakdown. At 4V, it is Zener breakdown. Between 4V and 7V, both types of breakdown will be available.
16. The interference source is generally divided into a voltage type and a current type interference source: the voltage type interference source is usually a digital signal itself and a digital power supply pin, and the current type interference source is usually a DC power supply.
17, CMOS gate circuit input impedance is very large, susceptible to static induction and breakdown, in addition to its internal protection circuit, should pay attention to electrostatic shielding during use and storage.
18. The Schmitt trigger can be connected to the ring oscillator output to shape the oscillating waveform and increase the anti-interference ability of the circuit.
19. PWM modulation technology can improve efficiency, but its inherent high-speed switching characteristics generate a lot of EMI interference. Even with very sophisticated filters to filter out these interferences, it is difficult to meet considerable EMI performance.
20, an experience of electronic engineers: digital device output clock jitter is too large, should not use the clock output provided by DSP or FPGA as much as possible, generally need to go through the phase-locked loop to multiply.
21. In high-speed CMOS systems, it is very common to use a CMOS IC device to drive the bus. However, the bus cannot be left floating during operation. The bus should be connected to VDD or VSS through a pull-up or pull-down resistor.
22. The working speed of the bus is related to the RC time constant formed by the related parasitic capacitance and the terminating resistor on the bus. The lower the terminal resistance, the faster the bus works, but the power consumption of the bus also increases. Unfortunately, , the two can not have both.
23, the use of high power supply voltage in CMOS logic circuit is also "good", because as the power supply voltage VDD increases, the device's noise margin will increase proportionally, the circuit work is more reliable, but The price to pay is that the power consumption of the device is therefore increased (PD = CL * VDD2 * f).
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